CCRID Product ProductLevel2 Title

2467337 ADW DBEDITOR Getting error while checking out any model in current working set in EDM.
2482683 ADW DBEDITOR Renaming a property in DBEditor for part classification with child is failing
2499425 ADW DBEDITOR EDM DB problem: Failure to change part classification while renaming
2493650 ADW LIBIMPORT Libimport: Schematic model classifications do not import properly
2501804 ADW LIB_FLOW Update the .dra templates in the installation directory
2419726 ALLEGRO_EDITOR 3D_CANVAS Via Drill for one of the stacked via is not shown in 3D Canvas
2458034 ALLEGRO_EDITOR 3D_CANVAS Mapping STEP file in 3D Mapper to a footprint with MM units causes scaling issue on instantiating to board in Mils.
2464357 ALLEGRO_EDITOR 3D_CANVAS Components are left out while bending in 3D Canvas
2465164 ALLEGRO_EDITOR 3D_CANVAS Cutout shape breaks bend in 3D Canvas
2467353 ALLEGRO_EDITOR 3D_CANVAS STEP with wrong dimensions in 3D mapper when board file is opened
2467744 ALLEGRO_EDITOR 3D_CANVAS When set to "Outer Layers", 3D Canvas does not show Soldermask for Package Geometry and Board Geometry.
2468007 ALLEGRO_EDITOR 3D_CANVAS Scaling issue in 3D Canvas with difference in design units and accuracy between DRA and BRD
2469087 ALLEGRO_EDITOR 3D_CANVAS Bend 4 is causing some issue, giving error message and crashing 3D viewer
2469091 ALLEGRO_EDITOR 3D_CANVAS Inner layer ignores the anchor point while working with 3D Canvas in bends
2469097 ALLEGRO_EDITOR 3D_CANVAS Bend thickness is different even after assigning the same radius.
2471670 ALLEGRO_EDITOR 3D_CANVAS Bbvia when stacked is not plated in 3D Canvas
2478875 ALLEGRO_EDITOR 3D_CANVAS STEP model size is wrong in new 3D mapper.
2480621 ALLEGRO_EDITOR 3D_CANVAS Models not scaled correctly when mapped at the symbol level
2483848 ALLEGRO_EDITOR 3D_CANVAS Release 17.4-2019: Plating is not shown on stacked vias in 3D Canvas
2491585 ALLEGRO_EDITOR 3D_CANVAS STEP model of wrong size in board when mapped to a footprint
2496349 ALLEGRO_EDITOR 3D_CANVAS STEP models are scaled with changed design accuracy
2498989 ALLEGRO_EDITOR 3D_CANVAS 3D STEP mapping scaling seems to be incorrect in 3D Canvas.
2503960 ALLEGRO_EDITOR 3D_CANVAS Scaling problem with STEP file mapping in 3D Canvas
2503973 ALLEGRO_EDITOR 3D_CANVAS Model is too small in 3D Canvas when STEP model is mapped in 3D Mapper
2505211 ALLEGRO_EDITOR 3D_CANVAS Exporting 3D pdf issue in release 17.4-2109: Symbols placed outside design
2505672 ALLEGRO_EDITOR 3D_CANVAS STEP output from 3D Canvas does not position symbols correctly for zones with bends
2526170 ALLEGRO_EDITOR 3D_CANVAS STEP Mapping in 3D Canvas still not stable: Model appears small in board
2530047 ALLEGRO_EDITOR 3D_CANVAS Missing dielectric shapes on stacked microvias
2020548 ALLEGRO_EDITOR DFM Cadence DFM customer site cannot submit requests
2020566 ALLEGRO_EDITOR DFM Error when sending Design True DFM Rules Request
2052907 ALLEGRO_EDITOR DFM The Submit Request button for DesignTrue DFM Rules Request does not work
2436381 ALLEGRO_EDITOR DFM Two fields are updated when changing "All via Pads" in DFF that should not be changed.
2500757 ALLEGRO_EDITOR DFM DRC showing on wrong layer
2121861 ALLEGRO_EDITOR DXF DXF_out does not export bottom pin numbers
2351006 ALLEGRO_EDITOR DXF Bottom Pin number missing in exported DXF
2490551 ALLEGRO_EDITOR INTERACTIV Pressing Shift after a Next command while adding a line is removing the added line segments.
2412066 ALLEGRO_EDITOR INTERFACES The Height of the header/footer text does not change when exporting PDF file
2500480 ALLEGRO_EDITOR PADS_IN PADS Import fails to translate and crashes the translator without any error message
2504300 ALLEGRO_EDITOR PAD_EDITOR In Padstack Editor summary, the mask layers data moves left by a row if octagon shape is used
1979586 ALLEGRO_EDITOR PLACEMENT Mirrored module becomes non mirrored after updating module from Place > Update Symbol > Module
2117354 ALLEGRO_EDITOR PLACEMENT Mirrored modules unmirrored after running Module Update
2496645 ALLEGRO_EDITOR SCRIPTS Allegro PCB Editor screen stops responding after importing sub-drawing.
2509697 ALLEGRO_EDITOR SHAPE Allegro PCB Editor crashes while generating the film area report
2500566 ALLEGRO_EDITOR SYMBOL Allegro PCB Editor crashes on loading symbol
2510647 ALLEGRO_EDITOR UI_FORMS Dynamic Etch Length Window goes behind Canvas
2489696 APD DFA Shape is covering the acid trap area, but "Copper Features: Minimum Acid traps Angle" DRC is still showing up.
2494093 APD DFA APD is flagging false DRCs for Acid Traps (DFM Checks) even when Traces and Vias are within shapes.
2493257 APD ORBITIO_IF IO cell pad is not imported by 'orbit import'
2336038 APD OTHER When updating only the nets in a finished design the Fillets will update as well causing problems
2506470 APD WLP WLP: Advanced Metal Fill leads to crash
2474872 CAPTURE PROJECT_MANAG OrCAD Capture crashes with the Make root command for Capture ONLY install
2485348 CAPTURE PROPERTY_EDIT Sorting is incorrect for property with value more than 10 digits in Property Editor
2502796 CONCEPT_HDL CORE Variant file corrupted when applying variant on 108 blocks in the design
2502919 ORBITIO OTHER OrbitIO: IO Info Placement does not work correctly when die origin is set to center
2503868 ORBITIO TCL OrbitIO does not accept multiple line Tcl command with /
2427201 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor - Allow any legal unit values for Pin Delay units, such as ns and ps
2442265 PCB_LIBRARIAN SYMBOL_EDITOR Delete PIN_TEXT in table creates a ? on symbol.
2499157 PCB_LIBRARIAN SYMBOL_EDITOR Symbol pins not visible in the Symbol Editor, seen in DE-HDL
2422442 PCB_LIBRARIAN SYMBOL_EDITOR New Symbol Editor - Copying and pasting pin-delay in pin table pastes unit to column right of pin delay
2413559 PSPICE TI_CONTRACT PSpice for TI runs slow with custom libs in pspice.ini
2478131 PSPICE TI_CONTRACT Setting simulation profile active takes a long time
2480069 PSPICE TI_CONTRACT PSpice for TI - GUI hangs when opening reference design
2490584 PSPICE TI_CONTRACT Editing simulation profile is very slow due to Online PSpice DRC
2498028 PSPICE TI_CONTRACT Parent case: 46506234- PSpice and memory management issue
2501408 PULSE ADHOC Open Projects - Default sort is not correct
2507051 PULSE ADHOC Commit with double quotes in message results in read-only design
2516926 PULSE CONFIGURATION Pulse - Cannot access link buttons with server URL being too long in sidebar
2509048 PULSE CORE Unable to place the migrated EDM Library Parts in System Capture
2526100 PULSE CORE Unified search not showing all Classifications and Parts
2526572 PULSE CORE Sub classification is missing when the searched in System Capture filter but present in DBEditor
2500261 PULSE UNIFIED_SEARC Cannot restrict the symbol selection based on PACK_TYPE from the library cell chips view
2501383 PULSE UNIFIED_SEARC Readability: Hyperlink color conflicts with selection color
2439368 PULSE VERSION_ON_SA User able to commit without taking updates available from another user
2501882 PULSE VERSION_ON_SA "Do you still want to commit forcefully" dialog default option leads user to pick the wrong choice
2507788 SIP_LAYOUT ASSY_RULE_CHE Unable to fix the Acute Angle Cover DRC's using the "Fix Issues" option
2510508 SIP_LAYOUT ASSY_RULE_CHE Applying Assembly Design Rule Check crashes APD Plus
2502364 SIP_LAYOUT STREAM_IF Hierarchical GDS Out issue
2484830 SPIF OTHER APR fails to route with Constraint region
2498612 SYSTEM_CAPTURE IMPORT_DEHDL_ Imported DE-HDL sheets missing connections for PWR symbols
2307488 SYSTEM_CAPTURE NAVLINKS Multiple issues with the Navigation Links in System Capture
2511357 SYSTEM_CAPTURE NEW_PROJECT New design from existing DE-HDL not importing correctly.
2525923 SYSTEM_CAPTURE PART_MANAGER Allegro System Capture - part manager fails to update parts when cell names contain special characters
2496178 SYSTEM_CAPTURE PERFORMANCE Software is lagging in response at times during editing sessions
2470460 SYSTEM_CAPTURE PRINT Print UI not showing all pages in the preview
2475002 SYSTEM_CAPTURE SMART_PDF Changing page in the print preview crashes System Capture
2475908 SYSTEM_CAPTURE SMART_PDF System Capture randomly crashes when printing a PDF
2489049 SYSTEM_CAPTURE SMART_PDF Random crash while printing schematic from System Capture
2487498 SYSTEM_CAPTURE VARIANT_MANAG Copying variant displays footprint incompatible message
2510422 TOPXP SWEEP_MANAGER Duplicate entries in the Connectivity Checker simulation result and number of simulations increases for writes
2497846 TOPXP SYSTEMSI Project archive does not include the external library models path
2504474 TOPXP TOPXPLORER IBIS Pin Mapping not correctly interpreted in some cases
Cadence OrCAD and Allegro 17.4-2019is a sleeker and more modern version of the OrCAD and Allegro release, with enhanced usability and a slew of new productivity- enhancing features. You get more intuitive and easy- to- use flows that enable optimized schematic- to- board- to- manufacturing transitions. So, whether you design schematics, work with physical layouts, manage or create libraries and parts, or administer ECAD processes, there are features in this release that will benefit you.
Starting with OrCAD and Cadence Allegro PCB - Tutorial for Beginners
Cadenceenables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry.
Product:Cadence SPB Allegro and OrCAD
Version:17.40.000-2019 HF020
Supported Architectures:x64
Website Home Page :www.cadence.com
Languages Supported:english
System Requirements:PC *
Software Prerequisites:Cadence SPB Allegro and OrCAD 17.40.000-2019 and above
Size:6.2 Gb

System Requirements:
OS:Windows 10 (64-bit) Professional, Windows Server 2012 (All Service Packs); Windows Server 2012 R2; Windows Server 2016.
CPU:Intel Core i7 4.30 GHz or AMD Ryzen 7 4.30 GHz with at least 4 cores
Memory:16 GB RAM
Space:50 GB free disk space (SSD drive is recommended)
Display:1920 x 1200 display resolution with true color (at least 32bit color)
GPU:A dedicated graphics card supporting OpenGL, minimum 2GB (with additional support for DX11 for 3D Canvas)
Monitors:Dual monitors (For physical design)
Supported MATLAB Version:R2019A-64Bit (For the PSpice-MATLAB interface)