New Features Introduced in HyperLynx VX.2.10
HyperLynx SI - Signal Integrity
HyperLynx SI VX.2.10 provides significant new capabilities for the design and verification of both high-speed serial (SerDes) links and DDR4/5 interfaces, along with improvements for general-purpose Signal Integrity.
HyperLynx PI - Power Integrity
HyperLynx PI VX.2.10 provides significant new capabilities for the design and verification of board-level Power Delivery Networks (PDNs), including board-level thermal co-simulation.
HyperLynx Advanced Solvers (3D EM)
HyperLynx Advanced Solvers VX.2.10 provides significant new capabilities for accurate 3D EM modeling of critical areas in high-speed systems designs.
HyperLynx DRC - Electrical Rule Checks
HyperLynx DRC VX.2.10 provides significant new capabilities for rapid checking of high-speed designs, including the ability to accelerate runs by distributing the verification task across multiple processors.

New HyperLynx Features by Product
HyperLynx SI/PI/Thermal - Overview
This release contains improvements in SERDES analysis, DDRx analysis, and DC Drop analysis, as well as some notable usability improvements
SERDES
- Taking advantage of the SERDES Compliance Wizard infrastructure improvements that were made in VX.2.8, HyperLynx VX.2.10 includes the addition of explicit support for over 70 new SERDES protocols. Furthermore, a new feature has been added for customers to add new protocols themselves.
- Reporting has been improved for clarity and consistency.
- When using the Compliance Wizard directly on S-parameters, those S-parameters can now be swept for solution space exploration.
- Standalone compliance/metric analysis in the Touchstone Viewer has been removed. The independent IBIS-AMI Wizard has also been removed. These capabilities have been consolidated into the SERDES Wizards.
- Automatic IBIS-AMI parameter optimization has been added to the SERDES IBISAMI Batch Wizard.
DDRx
- Can now sweep ACC and CLK buffer models in LineSim.
- Addition of ACC Overshoot measurements (per JEDEC spec).
- Support for diamond and hexagonal eye masks for DDR5 timing model development
PI Analysis
- New resistance matrix output in DC Drop analysis generates a matrix of resistances between sources and loads for resistance based PDN analysis
- Plating thickness and current constraints for vias can now be specified on a perpadstack basis.
General Usability
- New spreadsheet-based multi-board connection wizard allows for easier and more efficient setup of multi-board projects, especially those with complicated connector mappings. Connection mappings can be imported and exported for easy re-use between designs.
- Individual nets may now be selected for analysis in LineSim. This provides a dramatic performance improvement for very large schematics, including for analysis types like DDRx and SERDES.
HyperLynx DRC - Overview
HyperLynx DRC adds some important new functionality and defect fixes. The sections below provide details on some of the new capabilities.
Distributed verification
- By distributing Jobs on multiple CPUs or multiple PCs, run time is reduced, especially for large-scale verifications
- Work is distributed to each session on a rule-by-rule basis. The results are automatically aggregated into the hosting session.
- LSF can be used in an environment where LSF is set
- Setup is possible from Wizard
Database Compare
- A utility for Windows that uses External Automation. Detects the difference between the two designs.
- Example use cases are detecting differences in the design version or checkingwhether the reference design is completely copied to the target design.
New Rules
- Routing On/Off layer
- Trace shielding with stitching vias
- Via ani-pad integrity
Other major improvements
- DDR wizard is enhanced to be more robust.
- Many rules are enhanced to support more rule parameters for precise checking.
- Multiple custom rules can be complied in one step.
HyperLynx Advanced Solvers - Overview
The sections below provide details of new capabilities in this version of the HyperLynx Advanced Solvers products.
New Capabilities
- New multi-stack modeler operations
. Fast editing of objects
. Edit bond wires, solder balls, lead frames
. Sweep parameters
. Dozens of new context menu operations
. Better Filtering, Select Similar, Locate, etc.
. Automatic snap to grid and grid rendering
. Show 3D model for meshing
- Full-wave Solver Huygens' Box Import and Dipole Excitation
User Experience Improvement
- Fast edit mode for basic editing operations
- PDN Optimizer improvements / fixes.
- Improved launcher
- General Enhancements
. Technology dialog improvements (stack-up Areas tab, Table context menus & copying, etc.)
. Import designs (automatically add nets, etc.),
. Padstack/shape editing (, Span, etc.)
. Mesh and Solver options dialogs
. EMI shape editing
. Crop dialog usability
. Sync layout extents, displayed objects, layout options, etc.
- UI for new model operations
. Convert short arcs to Lines, enforce pins aspect ratio, group traces
. Recover hatch information, arc information,
. Remove area fill (hatching), remove holes from shapes
- Show 3D model for Meshing
Import & Export Improvements
- Universal Allegro Translator (UAT)
- UAT available for ODB++ (Windows and Linux)
- Complex via (CVP) import
Integration and Scripting Improvements
- Rigid Flex Flow improvements
HyperLynx 3D Explorer Improvements
- New template: Microstrip with Dk Control
- Sweep via padstack, start/end Layers
- Extend drill above/below support
- {{AUTO}} keyword for layer names
- Improved UI/UX: Recent templates, better layout, improved first-time experience
- Expert mode
- Better help (tooltips and HTML),
- Web browser enhancements (Back, Forward, Find, Zoom, Launch), etc.
Distributed Execution Improvements
- Job Distribution HyperLynx DRC rule verification support
- Job Distribution App support/simulate in cluster
- Distributed solve "Solve via PSH"
- PBS/Slurm/NC command line support
Accuracy and Solver Improvements
- Analysis of finite dielectric inclusions in layered medium
- Solver engine improvements can lead to 30-40% performance improvement
- New Excitations:
. Huygens Box excitations
. Dipole excitations
. Improved plane waves table
HyperLynx is an integrated family of analysis toolsfor high-speed digital design and verification. It makes state-of-the-art simulation available to a broad audience by combining advanced modeling and simulation techniques with automated flows that guide you through the process step by step.
HyperLynx combines ease of use with automated workflows to make high-speed design analysis accessible to mainstream system designers. This allows problems to be identified and resolved early in the design cycle. HyperLynx works with multiple PCB tools and is an ideal addition to any PCB design flow.
The HyperLynx family provides a complete analysis flow that combines best-practice design rule checking with comprehensive signal and power integrity simulation. Integrated 3D EM solvers create highly accurate interconnect models.
HyperLynx SI :Evaluate design tradeoffs with pre-layout analysis and validate designs prior to fab with post-layout analysis. Supports SerDes channels, DDRx memory interfaces, and general-purpose signal integrity.
HyperLynx Advanced Solvers:Integrated high-accuracy, high-capacity 3D electromagnetic simulation-full wave, quasi static, and hybrid solvers-with a common graphical interface for design editing and case management.
HyperLynx PI:Design and validate a board's power-delivery network (PDN) to meet impedance goals in an easy-to-use, "what-if" environment and optimize designs for cost and performance.
HyperLynx DRC:Fast, rules-based electrical design verification for PCB designers, system designers, and SI/PI/EMC experts, regardless of their layout tool or level of domain expertise.
The VX.2.10 release of HyperLynx provides significant new capabilities for the design and verification of high-speed serial (SerDes) links, DDRx interfaces, and board level Power Delivery Networks (PDNs).
What's New in VX.2.10 Release
Mentor Graphics Corporation, a Siemens business,is a world leader in electronic hardware and software design solutions, providing products, consulting services, and award-winning support for the world's most successful electronic, semiconductor, and systems companies. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.


HyperLynx VX.2.10 Compatible PCB Flows
All HyperLynx VX.2.10 products are fully compatible with the following PCB flows:
- Xpedition Enterprise VX.2.10
- Xpedition Package Integrator VX.2.10
- PADS VX.2.10
- PADS Professional VX.2.10
- Valor NPI v11.3
Generally, if you integrate to your layout tool (Siemens or 3rd-party) only through HYP, CCE, or ODB++ layout files, then HyperLynx SI/PI is very likely to work in all respects with your designs, even with pre-VX.2.2 versions of Xpedition or PADS / PADS-Professional. This is also applicable to BSXE V10. If you use a Siemens EDA PCB tool (Xpedition, PADS or PADS-Professional) and rely on "deeper" integration between HyperLynx and the PCB flow (for example, passing of data between Constraint Manager and LineSim/BoardSim), you should use HyperLynx VX.2.10 only with one of the specific VX.2.10 tool versions listed above.
One integration feature, use of the Analysis Control plug-in to run DC-drop simulations from directly within Xpedition Layout, is limited to the Xpedition Enterprise X-ENTP VX.2.10 flow and only on Windows
Supported Platforms
Overall Notes
- Specified patches below are minimum levels. Later versions of the patches are valid, supported configurations.
- Except as noted, all products are supported on all platforms.
- Processor and Memory requirements vary based on the mix of applications being used, the design complexity, and infrastructure requirements. Individual needs may vary from those published below.
HyperLynx-Specific Memory Recommendations
The following are general recommendations, based on typical usage. Memory consumption varies significantly depending on the size and other details of your designs. If you plan to use the following features, it is recommended that you install at least8 GB of RAM in your machine:
- Simulation sweeps (if a large number of parameter variations are enabled simultaneously)
- DDRx batch simulation under certain circumstances (especially with the "power-aware" option enabled)
For these features, 8 GB and preferably 16 GB are recommended:
- Power-integrity analysis of post-layout designs in BoardSim
- 3D EM simulation in the HyperLynx Full-Wave Solver (from either LineSim or BoardSim)
For this feature, 16 GB and possibly 32 GB are recommended:
- "Advanced decoupling analysis" using the new 2.5D power-integrity engine
In the sections below, the memory requirements do not assume use of these memory-intensive features
HyperLynx-Specific Graphics Processing Unit (GPU) Recommendations
We have tested OpenGL with a variety of hardware, operating system, graphics cards, and drivers and have not experienced any problems for many years. It should be noted that our products require graphics cards and drivers that support OpenGL version 1.3, 2.0, and 3.0. If any problems are encountered, we encourage you to go to the graphics card vendor website and download the latest version of the driver. If the issue persists, please contact customer support.
- 3D EM simulation in the HyperLynx Full-Wave Solver
Microsoft Windows 10 (Version 1909 and newer)
Microsoft Windows 10 (64-bit), Enterprise Edition and Pro Edition are supported.
While there is no known issue with running Microsoft Windows 10 Home Edition or Educational Edition, the product has not been tested with these editions, and therefore is not supported.
Kernel Configuration:N/A
Processor:Dual-core Intel or AMD processor minimum. See Processor Note for Intel/AMD Processors above.
Memory:8GB recommended
Swap Space:2x the amount of RAM
Windows Server 2016
Additional OS Patches (the following 64-bit configurations are supported):
- Microsoft Windows Server 2016, with all current updates via Windows Update
Warning: Windows Server 2016 does not by default include an internet web browser.
HyperLynx product documentation requires the installation of an internet web browser.
Windows Server 2016 users should download and install your choice of browsers (Edge,
Firefox or Chrome Browsers).
Processor:Dual-core Intel or AMD processor minimum. See Processor Note for Intel/AMD Processors above.
Memory:8 GB recommended (per simultaneously logged in user)
Swap Space:2X the amount of RAM
Windows Server 2019
Additional OS Patches (the following 64-bit configurations are supported):
- Microsoft Windows Server 2019, with all current updates via Windows Update
Processor:Dual-core Intel or AMD processor minimum. See Processor Note for Intel/AMD Processors above.
Memory:8 GB or more recommended (per simultaneously logged in user)
Swap Space:2X the amount of RAM